Methods and systems for terminating an iterative decoding process of a forward error correction block

ABSTRACT

The invention provides methods and systems for terminating an iterative decoding process of a Forward Error Correction block (FEC). The iterative decoding process of the FEC block is terminated upon determining that the FEC block cannot be decoded successfully. A method comprises calculating a metric based on one or more Log Likelihood Ratios (LLRs) corresponding to a first number of iterations of the iterative decoding process of the FEC block. The method further comprises, formulating one or more stopping criteria for the iterative decoding process based on a variation pattern of the metric over a second predetermined number of iterations of the iterative decoding process. The second predetermined number of iterations is a subset of the first number of iterations. Moreover, the method comprises terminating the iterative decoding process of the FEC block based on the one or more stopping criteria.

FIELD OF THE INVENTION

The present invention generally relates to communication systems. Morespecifically, the present invention relates to methods and systems forterminating an iterative decoding process of a forward error correction(FEC) block in a communication system.

BACKGROUND

Existing communication systems, such as those based on 3G, IEEE802.16/WIMAX standards, may use turbo codes as error correction codesfor encoding a data block to be transmitted. The data block can beencoded to obtain a Forward Error Correction (FEC) block. In a realscenario, the FEC block encoded using turbo codes can be transmittedfrom a transmitter to a receiver through a noisy channel. The FEC blockenables the receiver to receive the data block with reduced errorsdespite the noisy channel. Accordingly, the receiver may employ a turbodecoder system for decoding the FEC block received from the transmitter.

Typically, a turbo decoder system consists of two elementary decodersthat are serially concatenated. For example, the turbo decoder systemmay include two elementary decoders, referred to as decoder D1 anddecoder D2. Output of the decoders D1 can be output L1 and output of theelementary decoder D2 can be output L2. The output L1 and the output L2indicate soft information, such as a reliability of a bit being either 0or 1, related to bits of the FEC block received from the transmitter.Output L1 and output L2 can be used to calculate the Log LikelihoodRatios (LLRs). The LLRs are related to the probability of a bit in theFEC block to be a 0 or 1.

When the FEC block is received by the receiver, the FEC block is decodedby the decoder D1 to produce output L1. Further, the output L1 isprovided as an input to the decoder D2. Subsequently, the output L1 isdecoded by the decoder D2 to produce output L2.

The decoding of the FEC block is performed iteratively for ensuringcorrect decoding of the bits in the FEC block. In general, accuracy ofdecoding the FEC block by the turbo encoder system is high, if number ofiterations corresponding to the decoding of the FEC block is high.However, higher number of iterations for decoding the FEC block leads toan increase in power consumption and processing time of the turbodecoder system. Consequently, power consumption and throughput of theturbo decoder system may significantly be affected.

Several techniques have been proposed that terminate the iterativedecoding process as soon as the FEC block is deemed to be successfullydecoded. This reduces power consumption and improves the decoderprocessing throughput, for the case when the decoding of the FEC blockmay be eventually deemed successful. However, several FEC blocks may besignificantly corrupted which may result in unsuccessful decoding evenafter a large number of iterations. This can lead to wasteful powerconsumption by the turbo decoder system. Hence there is a need to reducethe number of iterations of the iterative decoding process of the FECblock at the turbo decoder system in such situations.

SUMMARY

An embodiment provides methods and systems for terminating an iterativedecoding process of a Forward Error Correction (FEC) block.

Further, an embodiment provides methods and systems for formulating oneor more stopping criteria for the iterative decoding process of the FECblock.

Another embodiment provides receiving a stopping indication for stoppingthe iterative decoding process of the FEC block.

Embodiments described above include calculating a metric based on one ormore Log Likelihood Ratios (LLRs) corresponding to a first number ofiterations of the iterative decoding process of the FEC block. Themetric can be a Mean Absolute Log-Likelihood Ratio (MALLR) calculated ateach iteration or one or more pairs of consecutive half iterations ofthe first number of iterations. Further, a predetermined number of bitsof the FEC block may be used to calculate the metric. Subsequently, oneor more stopping criteria are formulated for the iterative decodingprocess based on a variation pattern of the metric over a secondpredetermined number of iterations of the iterative decoding process.The second predetermined number of iterations is a subset of the firstnumber of iterations. Upon formulating the one or more stoppingcriteria, the iterative decoding process of the FEC block is terminatedwhen the one or more stopping criteria is met. The second predeterminednumber of iterations is a design parameter that can be chosen prior toor while performing the iterative decoding process of the FEC block.

In an embodiment, the one or more stopping criteria include checking aflatness of the variation pattern of the metric. Checking the flatnessof the variation pattern of the metric may include determining whether adifference between a minimum metric value and a maximum metric value ofthe metric over the second predetermined number of iterations is lessthan or equal to a first predefined threshold. Further, checking theflatness of the variation pattern of the metric may include checking ifan increment in the metric is less than or equal to a predefinedincrement threshold, checking if a ratio between two or more successivemetrics is less than or equal to a predefined successive ratiothreshold, checking if a local scope of the metric is less than or equalto a predefined local slope threshold and checking if a global slope ofthe metric is less than or equal to a predefined global threshold. Thelocal slope is computed over a third predetermined number of iterations,the third predetermined number of iterations being less than the secondpredetermined number of iterations. Moreover, the global slope iscomputed over the first number of iterations of the iterative decodingprocess. The first predefined threshold, the predefined incrementthreshold, the predefined successive ratio threshold, the predefinedlocal slope threshold, the predefined global threshold and the thirdpredetermined number of iterations are design parameters that can bechosen prior to or while performing the iterative decoding process ofthe FEC block.

In another embodiment, the one or more stopping criteria includeidentifying a non-increasing nature of the metric. The non-increasingnature of the metric includes checking over the second predeterminednumber of iterations of the iterative decoding process, if a netincrease in the metric is less than or equal to a second predefinedthreshold.

Embodiments described above further include receiving a stoppingindication that is generated based on one or more stopping criteria.Consequently, the iterative decoding process of the FEC block is stoppedupon receiving the stopping indication.

Embodiments described above further include, a device for terminatingthe iterative decoding process of the FEC block. The device comprises amemory and a processor operatively coupled to the memory. The memory isconfigured for storing one or more of a first predefined threshold, asecond predefined threshold, a predefined increment threshold, apredefined successive ratio threshold, a predefined local slopethreshold and a predefined global slope threshold. The processor isconfigured for calculating a metric using one or more LLRs pertaining toa first number of iterations of a predetermined number of bits of theFEC block. Further, the processor is configured for formulating one ormore stopping criteria for the iterative decoding process of the FECblock based on a variation pattern of the metric. Moreover, theprocessor is configured for terminating the iterative decoding processof the FEC block based on the one or more stopping criteria.

BRIEF DESCRIPTION OF DRAWINGS

A more complete appreciation of the present invention is provided byreference to the following detailed description when considered inconjunction with the accompanying drawings in which reference symbolsindicate the same or similar components, wherein

FIG. 1 illustrates an exemplary representation of an iterative decodingprocess of a Forward Error Correction (FEC) block at a turbo decoder, inaccordance with an embodiment.

FIG. 2 illustrates a flow diagram of a method for terminating aniterative decoding process of an FEC block, in accordance with anembodiment.

FIG. 3 illustrates a flow diagram of one or more stopping criteriaformulated for terminating an iterative decoding process of an FECblock, in accordance with an embodiment.

FIG. 4 illustrates a flow diagram of a method for stopping an iterativedecoding process of an FEC block, in accordance with an embodiment.

FIG. 5 illustrates a block diagram of a device for terminating aniterative decoding process of an FEC block, in accordance with anembodiment.

Skilled artisans will appreciate that elements in the figures areillustrated for simplicity and clarity and have not necessarily beendrawn to scale. For example, the dimensions of some of the elements inthe figures may be exaggerated relative to other elements to help toimprove understanding of embodiments of the present invention.

DETAILED DESCRIPTION OF THE DRAWINGS

While embodiments may be described in many different forms, some ofwhich are shown in the figures and described herein in detail, it isunderstood that the present disclosure is to be considered as an exampleof the principles of the present invention and not intended to limit theinvention to the specific embodiments shown and described. Further, theterms and words used herein are not to be considered limiting, butrather merely descriptive. It will also be appreciated that forsimplicity and clarity of illustration, common and well-understoodelements that are useful or necessary in a commercially feasibleembodiment may not be depicted in order to facilitate a less obstructedview of these various embodiments. Also, elements shown in the figureshave not necessarily been drawn to scale. For example, the dimensions ofsome of the elements are exaggerated relative to each other. Further,where considered appropriate, reference numerals have been repeatedamong the figures to indicate corresponding elements.

In this document, relational terms such as first and second, top andbottom, and the like may be used solely to distinguish one entity oraction from another entity or action without necessarily requiring orimplying any actual such relationship or order between such entities oractions. The terms “comprises,” “comprising,” or any other variationthereof, are intended to cover a non-exclusive inclusion, such that aprocess, method, article, or apparatus that comprises a list of elementsdoes not include only those elements but may include other elements notexpressly listed or inherent to such process, method, article, orapparatus. An element proceeded by “comprises . . . a” does not, withoutmore constraints, preclude the existence of additional identicalelements in the process, method, article, or apparatus that comprisesthe element.

It will be appreciated that embodiments of the present inventiondescribed herein may be comprised of one or more conventional processorsand unique stored program instructions that control the one or moreprocessors to implement, in conjunction with certain non-processorcircuits, some, most, or all of the functions of methods and systems forterminating an iterative decoding process of a Forward Error Correction(FEC) block described herein. The non-processor circuits may include,but are not limited to, a radio receiver, a radio transmitter, signaldrivers, clock circuits, power source circuits, and user input devices.As such, these functions may be interpreted as steps of a method forterminating an iterative decoding process of an FEC block.Alternatively, some or all functions could be implemented by a statemachine that has no stored program instructions, or in one or moreapplication specific integrated circuits (ASICs), in which each functionor some combinations of certain of the functions are implemented ascustom logic. Of course, a combination of the two approaches could beused. Thus, methods and means for these functions have been describedherein. Further, it is expected that one of ordinary skill,notwithstanding possibly significant effort and many design choicesmotivated by, for example, available time, current technology, andeconomic considerations, when guided by the concepts and principlesdisclosed herein will be readily capable of generating such softwareinstructions and programs and ICs with minimal experimentation.

Generally speaking, pursuant to various embodiments, methods and systemsfor terminating an iterative decoding process of an FEC block areprovided. The method comprises calculating a metric based on one or moreLog Likelihood Ratios (LLRs) that correspond to a first number ofiterations of the iterative decoding process of the FEC block. Further,one or more stopping criteria are formulated for the iterative decodingprocess with respect to a variation pattern of the metric over a secondpredetermined number of iterations of the iterative decoding process.Subsequently, the iterative decoding process of the FEC block isterminated based on the one or more stopping criteria.

Referring to the drawings and in particular to FIG. 1, an exemplaryrepresentation of an iterative decoding process of an FEC block at aturbo decoder 100 is shown in accordance with an embodiment. Atransmitter that wants to transmit data to a receiver may encode thedata using a turbo code to obtain an FEC block. The FEC block isreceived as an FEC block 102 at turbo decoder 100 of the receiver. Thoseskilled in the art will realize that if FEC block 102 is received over anoisy channel, then FEC block 102 may include some errors. Turbo decoder100 decodes FEC block 102 so as to detect and, in some embodiments,correct the errors in FEC block 102. If, FEC block 102 is estimated as asuccessfully decoded FEC block with respect to an independent successcriterion, the iterative decoding process of FEC block 102 may directlybe terminated. For instance, the independent success criterion can bechecking whether a minimum absolute LLR of the metric at a giveniteration of the first number of iterations exceeds a success threshold.The minimum absolute LLR of the metric is obtained over total number ofbits of the FEC block. If the minimum absolute LLR of the metric exceedsthe success threshold, the decoding of the FEC block may be deemedsuccessful and the iterative decoding process of the FEC block may,consequently, be terminated.

Referring back to FIG. 1, turbo decoder 100 includes two elementarydecoders such as decoder D1 104 and decoder D2 106 that are concatenatedserially. Decoder D1 104 decodes FEC block 102 to produce output L1 108.Subsequently, output L1 108 is provided as an input to decoder D2 106.Thereafter output L1 108 is used by decoder D2 106 to produce output L2110. Output L1 and output L2 may each include one or more real valuedentities, where real valued entities are real numbers. Moreover, FECblock 102 is iteratively decoded by providing output L2 110 as afeedback to decoder D1 104.

The process of decoding FEC block 102 by one of decoder D1 104 anddecoder D2 106 is referred to as a Half Iteration (HI). On the otherhand, the process of decoding FEC block 102 by decoder D1 104 first toobtain output L1 108 and then using this output L1 108 by decoder D2 106to obtain output L2 110 is referred to as a Full Iteration (FI). Any oneof an HI and a FI is referred to as an iteration hereinafter, unlessspecified otherwise.

When iteratively decoding FEC block 102 at turbo decoder 100, a metricis calculated based on one or more LLRs corresponding to a first numberof iterations. The one or more LLRs can be determined from the output L1108 and output L2 110 obtained at each iteration of the first number ofiterations of the iterative decoding process. The first number ofiterations can be the number of iterations performed till a given time.For instance, if 10 iterations are performed till a given time, then theLLRs can be determined at output L1 108 and output L2 110 of each of the10 iterations. The one or more LLRs indicate the likelihood of a bitfrom the plurality of bits in FEC block 102 to be a 0 or a 1.

Further, one or more stopping criteria are formulated based on avariation pattern of the metric for the iterative decoding process ofFEC block 102, over a second predetermined number of iterations of theiterative decoding process of the FEC block. Based on the one or morestopping criteria, the iterative decoding process of FEC block 102 isterminated at turbo decoder 100. The stopping criteria enables turbodecoder 100 to determine, after the first number of iterations, that FECblock 102 is so corrupted that further iterations may not result insuccessful decoding. This helps turbo decoder 100 to reduce powerconsumption and processing time, in the case when decoding FEC block 102fails.

Turning now to FIG. 2, a flow diagram of a method for terminating aniterative decoding process of an FEC block is shown, in accordance withan embodiment. Referring back to FIG. 1, FEC block 102 is received atturbo decoder 100. Subsequently, as mentioned earlier, one or more LLRsmay be determined for a first number of iterations of FEC block 102.Those skilled in the art will appreciate that a large positive valueassociated with an LLR may signify that a bit corresponding to that LLRcan be a 1. On the contrary, a large negative value of an LLR maysignify that a bit corresponding to that LLR can be a 0. In anembodiment, magnitude of an LLR indicates a reliability of a bit fromthe plurality of bits of FEC block 102 to be a 0 or a 1.

A metric is, then, calculated at 202 based on the one or more LLRscorresponding to a first number of iterations of the iterative decodingprocess of FEC block 102. In an embodiment, the metric is calculatedbased on a sum of absolute LLRs computed over the first number ofiterations of the iterative decoding process of the FEC block. Asmentioned earlier, the first number of iterations may include halfiterations and/or full iterations. The sum of absolute LLRs may denotesumming up of the one or more absolute LLRs of one or more bits of theFEC block calculated over each iteration of the first number ofiterations. For example, if the first number of iterations is 5, thenthe sum of absolute LLRs may be calculated at each of the 5 iterations,which can be 0.5^(th) iteration, 1^(st) iteration, 1.5^(th) iteration,2^(nd) iteration and 2.5^(th) iteration.

In another embodiment, the metric is a Mean Absolute Log-LikelihoodRatio (MALLR) corresponding to the first number of iterations of theiterative decoding process of FEC block 102. The MALLR can be calculatedusing the equation,

$\begin{matrix}{{MALLR} = {\frac{1}{N}{\sum\limits_{j = 1}^{N}{{{LLR}\left( {k,j} \right)}}}}} & (1)\end{matrix}$where,

N denotes total number of bits in FEC block 102;

LLR(k, j) denotes LLR of current k^(th) half iteration;

|x| denotes the absolute value of a number, x;

k denotes the iteration index that can take values such as 0.5, 1, 1.5,2, 2.5 . . . etc, where 0.5 corresponds to one HI, 1 corresponds to thefirst FI, 1.5 corresponds to the 3rd HI, and so on; and

j denotes a bit in FEC block 102.

According to an embodiment, the MALLR is computed over one or more pairsof successive half iterations belonging to the first number ofiterations of the iterative decoding process of FEC block 102. In anexemplary embodiment, the MALLR can be computed over one or more pairsof successive half iterations as follows:

$\begin{matrix}{{MALLR} = {{\frac{1}{2N}{\sum\limits_{j = 1}^{N}{{{LLR}\; 1\left( {k,j} \right)}}}} + {{{LLR}\; 2\left( {k,j} \right)}}}} & (2)\end{matrix}$Where,

LLR1(k, j) denotes LLR of bit j after iteration k included in the outputL1 108 of decoder D1 104 and

LLR2(k, j) denotes LLR of bit j after iteration k included in the outputL2 110 of decoder D2 106.

In yet another embodiment, one or more LLRs of a predetermined number ofbits of FEC block 102 are used for calculating the metric. For instance,if FEC block 102 includes 16 bits, LLRs of only 10 bits may be used tocalculate the metric, in order to limit the processing power andprocessing time. In yet another embodiment, the metric may be the one ormore LLRs of the predetermined number of bits of FEC block 102.

Subsequent to calculating the metric, one or more stopping criteria areformulated at 204 for the iterative decoding process based on avariation pattern of the metric over a second predetermined number ofiterations of the iterative decoding process. The second predeterminednumber of iterations is a subset of the first number of iterations.Moreover, the second predetermined number of iterations can include halfiterations and/or full iterations. For instance, the secondpredetermined number of iterations may be 3. Thus, the metric may beobserved till the variation pattern of the metric for at least 3iterations meets the one or more stopping criteria, after which theiterations may be stopped. Hence, in effect, the iterative decodingprocess can be stopped, when the variation pattern of the metric for atleast the last 3 iterations of the first number of iterations meets thestopping criteria.

In an embodiment, the one or more stopping criteria include checking aflatness of the variation pattern of the metric for the first number ofiterations. In this embodiment, if the variation pattern of the metricis approximately flat for at least the second predetermined number ofiterations of the iterative decoding process of FEC block 102, then astopping criterion may be considered to be met. In another embodiment,the one or more stopping criteria include identifying a non-increasingnature of the metric. In this embodiment, if the metric isnon-increasing for at least the second predetermined number ofiterations of the iterative decoding process of FEC block 102, thenanother stopping criterion may be considered to be met. The formulationof the one or more stopping criteria is explained in detail inconjunction with FIG. 3 described below. At 206, the iterative decodingprocess of FEC block 102 is terminated based on the one or more stoppingcriteria. Essentially, if the one or more stopping criteria are metafter the first number of iterations of FEC block 102, the iterativedecoding process of FEC block 102 is terminated at 206.

Turning now to FIG. 3, a flow diagram of one or more stopping criteriaformulated for terminating an iterative decoding process of an FECblock, in accordance with an embodiment is shown. Referring, inparticular, to FIG. 3A, at 302, the one or more stopping criteriaincludes checking a flatness of the variation pattern of the metric.Accordingly, in a first embodiment, at 304, it is determined, whether adifference between a minimum metric value and a maximum metric value ofthe metric over the second predetermined number of iterations is lessthan or equal to a first predefined threshold. For instance, after eachiteration, a difference between a minimum metric value and a maximummetric value over the last 3 iterations may be calculated. If thedifference is less than the first predefined threshold, then theiterative decoding process of FEC block 102 may be terminated. Else,another iteration may be performed and the difference may again bedetermined for the last 3 iterations. In this example, the secondpredetermined number of iterations is 3.

Those skilled in the art will realize that any method known in the artcan be used for determining if the difference between the minimum metricvalue and the maximum metric value of the metric is less than or equalto the first predefined threshold. In an embodiment, the firstpredefined threshold is defined based on a front end scaling factor or aSignal to Interference Noise Ratio (SINR) estimate for FEC block 102.

Further, in a second embodiment, it is checked, at 306, whether anincrement in the metric is less than or equal to a predefined incrementthreshold. For example, the predefined increment threshold may be equalto 4 and the number of iterations over which the increment in the metricneeds to be checked, which is essentially the second predeterminednumber of iterations, may be equal to 3. If the metrics calculated overthe last 4 iterations is equal to 20, 22, 24 and 26, then the incrementin the metric over each of the second predetermined number ofiterations, which is over the last 4 iterations, is equal to 2 which isless than the predefined increment threshold. Consequently, one of thestopping criteria is met and the iterative decoding process of FEC block102 may be terminated.

In a third embodiment, it is checked at 308 whether a ratio between twoor more successive metrics is less than or equal to a predefinedsuccessive ratio threshold. For example, the second predetermined numberof iterations may be 4 and the predefined successive ratio threshold maybe 0.9. Let the successive metrics calculated over the last fouriterations be equal to 20, 24, 30 and 34. It can be noted that the ratiobetween the first and the second successive metrics is 0.83. Similarly,the ratio between the other pairs of successive metrics is approximately0.8 and 0.89 respectively. Since the ratio between the successivemetrics calculated over the second predetermined number of iterations isless than the predefined successive ratio threshold of 0.9, one of thestopping criteria is met and the iterative decoding process of FEC 102may be terminated.

Further, in a fourth embodiment, it is checked at 310 whether a localslope of the metric is less than or equal to a predefined local slopethreshold. The local slope of the metric is computed over a thirdpredetermined number of iterations. The third predetermined number ofiterations is less than the second predetermined number of iterations.For example, let the second predetermined number of iterations be equalto 8 and the third predetermined number of iterations be equal to 2.Further, let the local slope of the metric computed over 2 iterations be0.25. If for instance, the predefined local slope threshold is 0.3, thecomputed local slope of the metric over 2 iterations is less than thepredefined local slope threshold. Accordingly, the iterative decodingprocess of FEC block 102 may be terminated.

Additionally, in a fifth embodiment, it is checked at 312 if a globalslope of the metric is less than or equal to a predefined globalthreshold. The global slope of the metric is a quantity computed at agiven iteration of the first number of iterations of the iterativedecoding process. Accordingly, if the quantity is less than or equal tothe predefined global threshold for the second predetermined number ofiterations, the iterative decoding process of FEC block 102 may beterminated. Further, it would be apparent to a person skilled in the artthat the one or more stopping criteria can be used in any combinationfor checking the flatness of the variation pattern of the metric.

Referring now to FIG. 3B, the one or more stopping criteria includesidentifying a non-increasing nature of the metric at 314. Foridentifying the non-increasing nature of the metric, it is checked at316, whether a net increase in the metric over the second predeterminednumber of iterations is less than or equal to a second predefinedthreshold. For instance, the second predetermined number of iterationsmay be 4 and the metric computed over the last 4 iterations may be equalto 15, 17, 18 and 22. Accordingly, it can be noted that the net increasein the metric over the second predetermined number of iterations is 7.If, for instance, the second predefined threshold for the net increaseis 10, it will be determined that the net increase in the metric overthe last 4 iterations is less than the second predefined threshold.Therefore, the iterative decoding process of FEC block 102 may beterminated.

Turning now to FIG. 4, a flow diagram of a method for stopping aniterative decoding process of FEC block 102 is illustrated in accordancewith an embodiment. As mentioned earlier, turbo decoder 100 decodes FECblock 102 using an iterative decoding process. At 402, a stoppingindication is received for stopping the iterative decoding process ofFEC block 102. In an embodiment, the stopping indication may be asignal. A stopping indication is generated based on one or more stoppingcriteria for the iterative decoding process of FEC block 102.

In an embodiment, the one or more stopping criteria include checking aflatness of a variation pattern of a metric, at 404. The metric iscalculated based on one or more LLRs corresponding to a first number ofiterations of a predetermined number of bits of FEC block 102.Calculation of the metric is described in detail in conjunction withFIG. 2. Further, in another embodiment, the one or more stoppingcriteria include identifying a non-increasing nature of the variationpattern of the metric, at 406. Thereafter, at 408, the iterativedecoding process of FEC block 102 is stopped upon receiving the stoppingindication.

In an embodiment, the metric is calculated after each iteration or apair of half iterations of the iterative decoding process of FEC block102. After each iteration or a pair of half iterations, it may bechecked if the variation pattern of the metric over a secondpredetermined number of iterations meets the one or more stoppingcriteria. The stopping indication may be generated as soon as thevariation pattern of the metric meets the one or more stopping criteria.

Referring now to FIG. 5, a block diagram of a device 500 for terminatingan iterative decoding process of FEC block 102 is shown, in accordancewith an embodiment. Device 500 includes a memory 502 and a processor 504operatively coupled to memory 502. Memory 502 is configured for storingone or more of a first predefined threshold, a second predefinedthreshold, a predefined increment threshold, a predefined successiveratio threshold, a predefined local slope threshold and a predefinedglobal threshold. The first predefined threshold, the second predefinedthreshold, the predefined increment threshold, the predefined successiveratio threshold, the predefined local slope threshold and the predefinedglobal threshold are system parameters fixed either prior to theiterative decoding process of FEC block 102 or based on a front endscaling factor or an SINR estimate for FEC block 102.

Further, processor 504 is configured for calculating a metric based onone or more LLRs corresponding to a first number of iterations of apredetermined number of bits of the FEC block. In an embodiment, themetric is an MALLR computed over the first number of iterations of theiterative decoding process of FEC block 102. In another embodiment, themetric is calculated based on a sum of absolute LLRs pertaining to thefirst number of iterations of the iterative decoding process of FECblock 102. In yet another embodiment, the metric may be the LLRs.

Further, processor 504 is configured for formulating one or morestopping criteria for the iterative decoding process of FEC block 102,based on a variation pattern of the metric over a second predeterminednumber of iterations of the iterative decoding process. As mentionedearlier, the second predetermined number of iterations is a subset ofthe first number of iterations.

For formulating the one or more stopping criteria, processor 504 isfurther configured for checking a flatness of the variation pattern ofthe metric and/or identifying a non-increasing nature of the variationof the metric. In an embodiment, for checking the flatness of thevariation pattern of the metric, processor 504 is further configured fordetermining whether a difference between a minimum metric value and amaximum metric value over the second predetermined number of iterationsis less than or equal to the first predefined threshold stored in memory502.

Moreover, processor 504 may also check the flatness of the variationpattern of the metric by checking whether an increment in the metric isless than or equal to the predefined increment threshold. Further,processor 504 may check whether a ratio between two or more successivemetrics is less than or equal to the predefined successive ratiothreshold. In an embodiment, processor 504 may check whether a localslope of the metric is less than or equal to the predefined local slopethreshold or a global slope of the metric is less than or equal to thepredefined global threshold. The local slope of the metric is computedover a third predetermined number of iterations. The third predeterminednumber of iterations being less than the second predetermined number ofiterations. Moreover, as mentioned earlier, the third predeterminednumber of iterations may be a subset of the second predetermined numberof iterations. Further, the global slope of the metric is computed overthe first number of iterations of the iterative decoding process.

Additionally, in an embodiment, for identifying the non-increasingnature of the variation pattern of the metric, processor 504 isconfigured for checking whether a net increase in the metric over thesecond predetermined number of iterations is less than or equal to asecond predefined threshold.

Further, when processor 504 detects that the one or more stoppingcriteria are met by the iterations of FEC block 102, processor 504 mayterminate the iterative decoding process of FEC block 102. Those skilledin the art will appreciate that termination of the iterative decodingprocess of an FEC block, which is received with a significant amount ofcorruption, results in reduction of power consumption and processingtime of the turbo decoder. This is due to the fact that if the FEC blockis received significantly low SNIR, then the turbo decoder may not beable to decode the FEC block correctly, even after performing severaldecoding iterations. Therefore, it is advantageous to terminate theiterative decoding process of the FEC block received with low SNIRearly, as it can be safely determined that proceeding further with theiterative decoding process may not help in decoding the FEC block.

The various embodiments described above provide methods and systems forterminating an iterative decoding process of a forward error correctionblock. The methods facilitate significant reduction in power consumptionof a turbo decoder when performing iterative decoding of FEC blocks.Additionally, number of iterations required for decoding an FEC block isreduced thereby minimizing decoding time of the FEC block. Further, asignificant increase in throughput of a turbo decoder can be achieved byemploying the abovementioned methods.

1. A method for terminating an iterative decoding process of a ForwardError Correction (FEC) block, the method comprising: calculating, in adecoder, a metric based on one or more Log Likelihood Ratios (LLRs)corresponding to a first number of iterations of the iterative decodingprocess of the FEC block; formulating, in the decoder, one or morestopping criteria for the iterative decoding process based on avariation pattern of the metric over a second number of iterations ofthe iterative decoding process, wherein the second number of iterationsis a subset of the first number of iterations; and terminating, in thedecoder, the iterative decoding process of the FEC block based on theone or more stopping criteria.
 2. The method of claim 1, wherein theterminating further comprises: estimating whether the FEC block is asuccessfully decoded FEC block, based on an independent successcriterion; and terminating the iterative decoding process when the FECblock is estimated to be the successfully decoded FEC block.
 3. Themethod of claim 1, wherein the first number of iterations and the secondnumber of iterations comprises at least one of a half iteration and afull iteration.
 4. The method of claim 1, wherein the metric is a MeanAbsolute Log-Likelihood Ratio (MALLR) corresponding to the first numberof iterations of the iterative decoding process of the FEC block.
 5. Themethod of claim 4, wherein the MALLR is computed over one or more pairsof successive half iterations of the iterative decoding process of theFEC block, the one or more pairs of successive half iterations belongingto the first number of iterations.
 6. The method of claim 1, wherein themetric is a sum of absolute LLRs corresponding to the first number ofiterations of the iterative decoding process of the FEC block.
 7. Themethod of claim 1, wherein the metric is calculated from the one or moreLLRs of a predetermined number of bits of the FEC block.
 8. The methodof claim 1, wherein the one or more stopping criteria comprises checkinga flatness of the variation pattern of the metric, wherein checking aflatness of the variation pattern of the metric comprises: determiningover the second number of iterations of the iterative decoding process,whether a difference between a minimum metric value and a maximum metricvalue of the metric is less than or equal to a first predefinedthreshold.
 9. The method of claim 8, wherein the first predefinedthreshold is based on at least one of a front end scaling factor and aSignal to Interference Noise Ratio (SINR) estimate corresponding to theFEC block.
 10. The method of claim 1, wherein the one or more stoppingcriteria comprises checking a flatness of the variation pattern of themetric, wherein checking a flatness of the variation pattern of themetric comprises: checking whether an increment in the metric is lessthan or equal to a predefined increment threshold; checking whether aratio between two or more successive metrics is less than or equal to apredefined successive ratio threshold; checking whether a local slope ofthe metric is less than or equal to a predefined local slope threshold,the local slope being computed over a third number of iterations,wherein the third number of iterations is less than or equal to thesecond number of iterations; and checking whether a global slope of themetric is less than or equal to a predefined global threshold, theglobal slope being computed over the first number of iterations of theiterative decoding process.
 11. The method of claim 1, wherein the oneor more stopping'criteria comprises identifying a non-increasing natureof the metric, identifying a non-increasing nature of the metriccomprising: checking, over the second number of iterations of theiterative decoding process, whether a net increase in the metric is lessthan or equal to a second predefined threshold.
 12. The method of claim1, wherein calculating the metric includes calculating the metric ateach iteration of the first number of iterations.
 13. The method ofclaim 1, wherein a number of the second number of iterations isdetermined during the iterative decoding process.
 14. A method forstopping an iterative decoding process of a Forward Error Correction(FEC) block, the method comprising: receiving, at a decoder, a stoppingindication, the stopping indication being generated based on one or morestopping criteria, wherein the one or more stopping criteria includes:identifying, in a decoder, a non-increasing nature of a variationpattern of a metric by checking, over a second number of iterations ofthe iterative decoding process, whether a net increase in the metric isless than or equal to a predefined threshold, the metric beingcalculated based on one or more Log Likelihood Ratios (LLRs)corresponding to a first number of iterations of a predetermined numberof bits of the FEC block; and stopping the iterative decoding process ofthe FEC block based on the stopping indication.
 15. A device forterminating an iterative decoding process of a Forward Error Correction(FEC) block, the device comprising: a memory configured to store atleast one of a first predefined threshold, a second predefinedthreshold, a predefined increment threshold, a predefined successiveratio threshold, a predefined local slope threshold, and a predefinedglobal threshold; and a processor operatively coupled to the memory, theprocessor configured to calculate a metric based on a Log LikelihoodRatio (LLR) corresponding to a first number of iterations of apredetermined number of bits of the FEC block; formulate one or morestopping criteria for the iterative decoding process of the FEC blockbased on a variation pattern of the metric over a second number ofiterations of the iterative decoding process, wherein the second numberof iterations is a subset of the first number of iterations; andterminate the iterative decoding process of the FEC block based on theone or more stopping criteria.
 16. The device of claim 15, wherein theprocessor is further configured to check a flatness of the variationpattern of the metric; or identify a non-increasing nature of thevariation pattern of the metric.
 17. The device of claim 16, wherein, tocheck the flatness of the variation pattern of the metric, the processoris further configured to determine, over the second predetermined numberof iterations of the iterative decoding process, whether a differencebetween a minimum metric value and a maximum metric value of the metricis less than or equal to the first predefined threshold, wherein thefirst predefined threshold is based on at least one of a front endscaling factor and a Signal to Interference Noise Ratio (SINR) estimatecorresponding to the FEC block.
 18. The device of claim 16, wherein, tocheck the flatness of the variation pattern of the metric, the processoris further configured to check whether an increment in the metric isless than or equal to the predefined increment threshold; check whethera ratio between two or more successive metrics is less than or equal tothe predefined successive ratio threshold; check whether a local slopeof the metric is less than or equal to the predefined local slopethreshold, the local slope being computed over a third number ofiterations wherein the third number of iterations is less than or equalto the second number of iterations; and check whether a global slope ofthe metric is less than or equal to the predefined global threshold, theglobal slope being computed over the first number of iterations of theiterative decoding process.
 19. The device of claim 16, wherein, toidentify the non-increasing nature of the variation pattern of themetric, the processor is further configured to check, over the secondnumber of iterations of the iterative decoding process, whether a netincrease in the metric is less than or equal to a second predefinedthreshold.
 20. The device of claim 15, wherein the processor isconfigured to calculate the metric at each iteration of the first numberof iterations.
 21. The device of claim 15, wherein a number of thesecond number of iterations is determined during the iterative decodingprocess.